timescale in verilog

The timescale directive in Verilog used to model hardware is quite confusing, most people I have interacted with most times do not understand or are just ignorant of the timescale directive. So I thought I should jot this one down so that next time I meet up with people ignorant of this, I can point them to this post!

The directive is used to model delays in signal assertions with specific precision. Unlike vhdl, which has specific time unit constructs [ns(nanosecond), ps(picosecond), ms(millisecond)] Verilog inherently does NOT support these data-types and hence there is no time unit. The unit and the precision is specified using the timescale directive.

Aan example Verilog codes would feature this directive as
`timescale 1ns/100ps
which is in the format `timescale time_units / time_precision

  A#100 in verilog is used to identify 100 units of time. For instance, with a `timescale of 1ns/100ps

  Avalue of #21.375 is indicated as

21.375 * 1 ns = 21.375 ns and the .375 is rounded off to the next 100ps ~ 400ps.

so #21.375 is taken as 21.4ns

If the timescale is set to 1ns / 10ps, the precision is higher and so the math is 21.375 * 1ns = 21.375 and then the .375 is rounded to the next 10th pico second which is 380 ps

So a #21.375 ~ 21.380 ps in this case.

--
shyam